1. Field of the Invention
The present invention relates to a circuit configuration with an integrated amplifier.
For example, it is common in sensor technology to capture a measuring signal in a remote sensor, amplify it and transmit it over a transmission line to evaluating electronics, which can be centrally disposed. It is also customary therein for the sensor to receive its operating voltage from the central unit, likewise over lines.
It may be desirable, for instance for reasons of operational reliability, to be able to detect an interruption of a supply line from the central unit to the remote sensor with the aid of the measuring signal, for instance in the central unit. Otherwise, given an error in the supplying of the sensor, it could provide a signal that could be misinterpreted as a measured signal.
A known technique given an interruption, for instance a break of a supply line, is to create a low-impedance connection from the output terminal of the sensor, which can provide a measuring signal, to the supply voltage terminals at the sensor. Thus, in the central unit it is possible to detect a failure in that the potential of the output signal is above an upper potential limit or below a lower potential limit that typically occur in normal operation.
Published, Non-Prosecuted German Patent Application DE 44 00 437 A1 describes a semiconductor sensor device. There, given an interruption of a voltage supply terminal, a value outside a predefined range is outputted at the output by a clipper.
2. Summary of the Invention
It is accordingly an object of the invention to provide a circuit configuration with an integrated amplifier which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which makes possible, in a simple and reliable fashion, the detection of a failure such as an interruption of a supply voltage supplying the circuit configuration.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration. The circuit has an integrated amplifier with a symmetrical amplifier output, a supply potential terminal to be coupled to a voltage source for supplying an operating current, a reference potential terminal to be coupled to the voltage source, a tri-state output, and an output stage having a pair of complementary output transistors with control inputs connected to the symmetrical amplifier output. The pair of complementary output transistors includes a first output transistor having a controlled path coupling the supply potential terminal to the tri-state output, and a second output transistor having a controlled path coupling the tri-state output to the reference potential terminal. The output stage further has switches coupling the first and second output transistors with the tri-state output so that the tri-state output is put into a high-impedance state given an interruption of the operating current.
To couple the output transistors with the tri-state output, a blocking circuit can be provided, which is driven by a driver circuit, which is connected to the reference and supply potential terminals for its current supply. During normal operation, the blocking circuit can effectuate a low-impedance coupling of the output transistors with the tri-state output. But if a disturbance such as an interruption of the current supply occurs, then a high-impedance coupling of the output transistors with the tri-state output is effectuated with the aid of the driver circuit.
The input of the amplifier can be connected to the output of a sensor.
The circuit configuration can be coupled with a voltage source, which can be connected by lines.
The amplifier output can be laid out symmetrically, i.e. for conducting a difference signal. Such a difference signal is customarily carried on two lines.
During normal operation of the circuit configuration, the output stage at the tri-state output can provide a digital signal or an analog signal at its output, depending on the signal on the input side, for instance the measuring signals of a sensor. The digital signal can be a binary signal, which can have two states, low and high. The logic states are customarily coded by respective voltage values or voltage ranges.
In the normal operation of the circuit configuration, the signal levels that can arise are within a defined range, which can have lower and upper limits.
The normal operation of the circuit configuration is interrupted by the interruption of the operating-current supply, for example. In this case, in the described circuit configuration the tri-state output is put into a high-impedance state. This can be easily detected in that the signal available at the tri-state output, with respect to its voltage level or potential, is above an upper voltage or below a lower voltage occurring in normal operation. In order to accomplish this, a load resistance can be connected to the tri-state output. The load resistance can be connected to the tri-state output via one terminal and to a reference or supply potential terminal via another terminal. This is of course predicated on the condition that the tri-state output has a substantially higher-impedance than the load resistance connected to it.
If the load resistance is connected to the reference potential terminal with its additional terminal, it draws the tri-state output to the reference potential given an interruption of the operating-current supply. The load instance can be referred to as a pull-down load instance. If, on the other hand, the load resistance is connected between the supply potential terminal and the tri-state output, then given an interruption of the operating-current supply of the circuit configuration, the tri-state output is drawn to the supply potential.
The described circuit configuration is well suited to integration in an integrated circuit. In an integrated circuit, the amplifier and the sensor that is connected to the amplifier on the input side can be integrated, as can the output stage. The voltage source for supplying the circuit configuration can be disposed in a central unit, in which the load resistance can also be provided. Furthermore, a converting and evaluating circuit can also be provided in the central unit, which, in a normal operation of the circuit, continually compares the potential at the tri-state output of the output stage to an upper and lower limit, and emits a signal indicating a disturbance when a limit is crossed.
The described circuit configuration has a number of advantages over a circuit configuration whose output stage provides a low-impedance output given the interruption of an operating-current supply of the circuit. Self-conducting transistor structures are usually required therein, which are not provided in the majority of known manufacturing processes for semiconductor circuits and therefore require additional implantation steps. In contrast, in the present circuit configuration, self-blocking transistors can be utilized in the output stage, which are usually present in BiCMOS or CMOS processes.
In the event of a failure, a high-impedance output of the output stage makes it possible to better differentiate a failure state from the normal operating state. Furthermore, self-blocking transistors do not lead to a transient pulse when the circuit configuration is powered up. Beyond this, the current consumption of the circuit in the event of failure is relatively small.
When the load resistance is interposed between the supply potential terminal and the tri-state output, the potential at the tri-state output is equal to the supply potential given the interruption either of the line connecting the voltage source and the supply potential terminal or of the line connecting the reference potential terminal and the supply voltage source, or when both lines are interrupted. If, on the other hand, the load resistance is connected between the tri-state output and the reference potential terminal, then the potential at the tri-state output is equal to the reference potential, i.e. zero volts, regardless of the load instance. Thus, only a comparator is needed in the evaluation circuit in order to be able to detect a disturbance such as an interruption of a supply line, which saves additional costs. In addition, the present circuit can easily be built to be secure against mispoling; i.e. in such a way that the circuit configuration cannot be damaged by confusing a supply potential terminal with the tri-state output or the reference potential terminal with the tri-state output and/or confusing the reference and supply voltage terminals.
The tri-state output can provide a measuring signal, for instance the output signal of a sensor, at the output of the output stage as an analog signal.
In order to guarantee that only potential values below a maximum value and above a minimum value arise at the tri-state output during normal operation, a switching stage can be provided, which guarantees that the potential at the tri-state output is within predefined limits during normal operation. If an evaluation circuit nevertheless detects a crossing of the upper or lower potential limit, then this is an unambiguous indication that a line break or interruption of the operating-current supply of the circuit configuration has occurred.
In a preferred embodiment of the invention, a pair of complementary blocking transistors is provided in the output stage as the switch, a first of which is interposed with its controlled path between the first output transistor and the tri-state output, and the second of which is interposed with its controlled path between the tri-state output and the second output transistor. Charge pump circuits are provided, which are connected on the input side to supply and reference potential terminals and on the output side to the control inputs of the blocking transistors. The blocking transistors are low-impedance conductive in the normal mode owing to the charge pump circuits. To accomplish this, the charge pump circuit of the first blocking transistor can provide a voltage at its output which is 3 volts over the supply potential, and the charge pump circuit connected to the second blocking transistor can provide a potential value at its output which is 3 volts smaller than the reference potential. But if the supply voltage, i.e. the operating-current supply of the circuit configuration, is interrupted, the charge pump circuits as well are no longer powered on the input side, so that the two blocking transistors block; i.e. their controlled systems are high-impedance. A tri-state output can be thereby achieved whose high-impedance state occurs in the range of several giga ohms. This guarantees that in the event of a failure the tri-state output assumes a potential that is very close to the reference potential or the supply potential, regardless of how the load resistance is connected. Accordingly, with the described circuit configuration a reliable detection of a failure such as a line break is possible.
The charge pump circuits are intended to provide a potential on the output side in a normal operation whose magnitude exceeds the respectively allocated supply potential by at least a few transistor threshold voltagesxe2x80x94provided that the blocking transistors are constructed as self-conducting transistors. The first charge pump circuit is intended to provide a potential which exceeds the potential made available at the supply potential terminal by several threshold voltages, and the second charge pump circuit is intended to provide a potential on the output side which exceeds the potential at the reference potential terminal by several threshold voltages.
In another preferred embodiment of the invention, the blocking transistors are self-blocking MOS transistors.
To the extent that the circuit is realized with blocking transistors that include troughs, the troughs of the blocking transistors are preferably not resistively connected to the tri-state output.
In another preferred embodiment of the invention, the first blocking transistor is an NMOS transistor, and the second blocking transistor is a PMOS transistor. The first blocking transistor can be constructed as an NMOS transistor whose gate terminal is raised above a positive supply potential in the normal operation of the circuit with the charge pump circuit. The second blocking transistor can be a PMOS transistor whose gate terminal receives a provided potential below the reference potential during normal operation with a charge pump circuit.
In another preferred embodiment of the invention, the voltage source is an external voltage source which is connected to the supply and reference potential terminals. The voltage source can be provided in a central unit, which may include a load resistance as well as a converting and evaluating circuit. A number of circuit configurations with an integrated amplifier and output stage can be connected to the central unit over respective long lines.
In another preferred embodiment of the invention, an external electrical load is provided, which is connected via one terminal to the tri-state output and via a second terminal to the supply or reference potential terminal. The external electrical load can be connected via the additional terminal directly to the voltage source that supplies the circuit configuration with operating current.
In another advantageous embodiment of the invention, a converting and evaluating circuit is provided, which is connected to the tri-state output on the one hand and to the reference potential terminal on the other hand. The converting and evaluating circuit is connected to the supply potential terminal for referencing and monitors the potential at the tri-state output as to whether it is in a range which is permissible in a normal operation. The range that is permissible during normal operation can be defined by upper and lower voltage limits. The comparison of the signal provided at the tri-state output to the range limits defining the permissible range during normal operation can be accomplished by a comparator that is provided in the converting and evaluating circuit.
In another advantageous embodiment of the invention, the first output transistor includes a PMOS or pnp transistor, and the second output transistor includes an NMOS or npn transistor. IQ Care must be taken that neither an n-trough in which the self-blocking PMOS transistor is formed nor a p-trough in which the self-blocking NMOS transistor is formed is connected to the tri-state output.
In another preferred embodiment of the invention, the output stage is constructed as a circuit that is integrated in a p-doped substrate. The reference potential terminal can be connected to the p-substrate, particularly to a p-substrate terminal. The integrated circuit can be produced in a true two-trough procedure.
In another preferred embodiment, the output stage is constructed as a circuit that is integrated in an n-doped substrate. An n-substrate terminal can be connected to the supply potential terminal. The integrated circuit can be produced in a true two-trough procedure.
In another preferred embodiment of the invention, a high-impedance resistance is provided, which is interposed between the supply potential terminal and the reference potential terminal. Such a high-impedance resistance, which can equal one mega ohm, for instance, is customarily present in integrated CMOS or BiCMOS circuits anyway. What is important is that this resistance have a significantly greater conductivity than that of a blocking pn-junction that is formed parallel thereto. The additional high-impedance resistance improves the high-impedance character of the tri-state output in the event of a failure, particularly at high temperatures. The high-impedance resistance can be constructed as a self-conducting transistor.
In another preferred embodiment of the present invention, the total effective electrical resistance between the supply potential terminal and the reference potential terminal equals 1 mega ohm. If the circuit as a whole is built in CMOS circuitry, an additional resistance, preferably of 1 mega ohm, can be inserted between the supply potential and reference potential terminals, because in this case a cross-current due to parasitic effects will not flow anyway. This improves the reliability of the circuit.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration with an integrated amplifier, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.